// +build l1xx_md

// Peripheral: RCC_Periph  Reset and Clock Control.
// Instances:
//  RCC  mmap.RCC_BASE
// Registers:
//  0x00 32  CR        Clock control register.
//  0x04 32  ICSCR     Internal clock sources calibration register.
//  0x08 32  CFGR      Clock configuration register.
//  0x0C 32  CIR       Clock interrupt register.
//  0x10 32  AHBRSTR   AHB peripheral reset register.
//  0x14 32  APB2RSTR  APB2 peripheral reset register.
//  0x18 32  APB1RSTR  APB1 peripheral reset register.
//  0x1C 32  AHBENR    AHB peripheral clock enable register.
//  0x20 32  APB2ENR   APB2 peripheral clock enable register.
//  0x24 32  APB1ENR   APB1 peripheral clock enable register.
//  0x28 32  AHBLPENR  AHB peripheral clock enable in low power mode register.
//  0x2C 32  APB2LPENR APB2 peripheral clock enable in low power mode register.
//  0x30 32  APB1LPENR APB1 peripheral clock enable in low power mode register.
//  0x34 32  CSR       Control/status register.
// Import:
//  stm32/o/l1xx_md/mmap
package rcc

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	HSION    CR = 0x01 << 0  //+ Internal High Speed clock enable.
	HSIRDY   CR = 0x01 << 1  //+ Internal High Speed clock ready flag.
	MSION    CR = 0x01 << 8  //+ Internal Multi Speed clock enable.
	MSIRDY   CR = 0x01 << 9  //+ Internal Multi Speed clock ready flag.
	HSEON    CR = 0x01 << 16 //+ External High Speed clock enable.
	HSERDY   CR = 0x01 << 17 //+ External High Speed clock ready flag.
	HSEBYP   CR = 0x01 << 18 //+ External High Speed clock Bypass.
	PLLON    CR = 0x01 << 24 //+ PLL enable.
	PLLRDY   CR = 0x01 << 25 //+ PLL clock ready flag.
	CSSON    CR = 0x01 << 28 //+ Clock Security System enable.
	RTCPRE   CR = 0x03 << 29 //+ RTC/LCD Prescaler.
	RTCPRE_0 CR = 0x01 << 29 //  Bit0.
	RTCPRE_1 CR = 0x02 << 29 //  Bit1.
)

const (
	HSIONn  = 0
	HSIRDYn = 1
	MSIONn  = 8
	MSIRDYn = 9
	HSEONn  = 16
	HSERDYn = 17
	HSEBYPn = 18
	PLLONn  = 24
	PLLRDYn = 25
	CSSONn  = 28
	RTCPREn = 29
)

const (
	HSICAL     ICSCR = 0xFF << 0  //+ Internal High Speed clock Calibration.
	HSITRIM    ICSCR = 0x1F << 8  //+ Internal High Speed clock trimming.
	MSIRANGE   ICSCR = 0x07 << 13 //+ Internal Multi Speed clock Range.
	MSIRANGE_0 ICSCR = 0x00 << 13 //  Internal Multi Speed clock Range 65.536 KHz.
	MSIRANGE_1 ICSCR = 0x01 << 13 //  Internal Multi Speed clock Range 131.072 KHz.
	MSIRANGE_2 ICSCR = 0x02 << 13 //  Internal Multi Speed clock Range 262.144 KHz.
	MSIRANGE_3 ICSCR = 0x03 << 13 //  Internal Multi Speed clock Range 524.288 KHz.
	MSIRANGE_4 ICSCR = 0x04 << 13 //  Internal Multi Speed clock Range 1.048 MHz.
	MSIRANGE_5 ICSCR = 0x05 << 13 //  Internal Multi Speed clock Range 2.097 MHz.
	MSIRANGE_6 ICSCR = 0x06 << 13 //  Internal Multi Speed clock Range 4.194 MHz.
	MSICAL     ICSCR = 0xFF << 16 //+ Internal Multi Speed clock Calibration.
	MSITRIM    ICSCR = 0xFF << 24 //+ Internal Multi Speed clock trimming.
)

const (
	HSICALn   = 0
	HSITRIMn  = 8
	MSIRANGEn = 13
	MSICALn   = 16
	MSITRIMn  = 24
)

const (
	SW          CFGR = 0x03 << 0  //+ SW[1:0] bits (System clock Switch).
	SW_0        CFGR = 0x01 << 0  //  Bit 0.
	SW_1        CFGR = 0x02 << 0  //  Bit 1.
	SW_MSI      CFGR = 0x00 << 0  //  MSI selected as system clock.
	SW_HSI      CFGR = 0x01 << 0  //  HSI selected as system clock.
	SW_HSE      CFGR = 0x02 << 0  //  HSE selected as system clock.
	SW_PLL      CFGR = 0x03 << 0  //  PLL selected as system clock.
	SWS         CFGR = 0x03 << 2  //+ SWS[1:0] bits (System Clock Switch Status).
	SWS_0       CFGR = 0x01 << 2  //  Bit 0.
	SWS_1       CFGR = 0x02 << 2  //  Bit 1.
	SWS_MSI     CFGR = 0x00 << 2  //  MSI oscillator used as system clock.
	SWS_HSI     CFGR = 0x01 << 2  //  HSI oscillator used as system clock.
	SWS_HSE     CFGR = 0x02 << 2  //  HSE oscillator used as system clock.
	SWS_PLL     CFGR = 0x03 << 2  //  PLL used as system clock.
	HPRE        CFGR = 0x0F << 4  //+ HPRE[3:0] bits (AHB prescaler).
	HPRE_0      CFGR = 0x01 << 4  //  Bit 0.
	HPRE_1      CFGR = 0x02 << 4  //  Bit 1.
	HPRE_2      CFGR = 0x04 << 4  //  Bit 2.
	HPRE_3      CFGR = 0x08 << 4  //  Bit 3.
	HPRE_DIV1   CFGR = 0x00 << 4  //  SYSCLK not divided.
	HPRE_DIV2   CFGR = 0x08 << 4  //  SYSCLK divided by 2.
	HPRE_DIV4   CFGR = 0x09 << 4  //  SYSCLK divided by 4.
	HPRE_DIV8   CFGR = 0x0A << 4  //  SYSCLK divided by 8.
	HPRE_DIV16  CFGR = 0x0B << 4  //  SYSCLK divided by 16.
	HPRE_DIV64  CFGR = 0x0C << 4  //  SYSCLK divided by 64.
	HPRE_DIV128 CFGR = 0x0D << 4  //  SYSCLK divided by 128.
	HPRE_DIV256 CFGR = 0x0E << 4  //  SYSCLK divided by 256.
	HPRE_DIV512 CFGR = 0x0F << 4  //  SYSCLK divided by 512.
	PPRE1       CFGR = 0x07 << 8  //+ PRE1[2:0] bits (APB1 prescaler).
	PPRE1_0     CFGR = 0x01 << 8  //  Bit 0.
	PPRE1_1     CFGR = 0x02 << 8  //  Bit 1.
	PPRE1_2     CFGR = 0x04 << 8  //  Bit 2.
	PPRE1_DIV1  CFGR = 0x00 << 8  //  HCLK not divided.
	PPRE1_DIV2  CFGR = 0x04 << 8  //  HCLK divided by 2.
	PPRE1_DIV4  CFGR = 0x05 << 8  //  HCLK divided by 4.
	PPRE1_DIV8  CFGR = 0x06 << 8  //  HCLK divided by 8.
	PPRE1_DIV16 CFGR = 0x07 << 8  //  HCLK divided by 16.
	PPRE2       CFGR = 0x07 << 11 //+ PRE2[2:0] bits (APB2 prescaler).
	PPRE2_0     CFGR = 0x01 << 11 //  Bit 0.
	PPRE2_1     CFGR = 0x02 << 11 //  Bit 1.
	PPRE2_2     CFGR = 0x04 << 11 //  Bit 2.
	PPRE2_DIV1  CFGR = 0x00 << 11 //  HCLK not divided.
	PPRE2_DIV2  CFGR = 0x04 << 11 //  HCLK divided by 2.
	PPRE2_DIV4  CFGR = 0x05 << 11 //  HCLK divided by 4.
	PPRE2_DIV8  CFGR = 0x06 << 11 //  HCLK divided by 8.
	PPRE2_DIV16 CFGR = 0x07 << 11 //  HCLK divided by 16.
	PLLSRC      CFGR = 0x01 << 16 //+ PLL entry clock source.
	PLLSRC_HSI  CFGR = 0x00 << 16 //  HSI as PLL entry clock source.
	PLLSRC_HSE  CFGR = 0x01 << 16 //  HSE as PLL entry clock source.
	PLLMUL      CFGR = 0x0F << 18 //+ PLLMUL[3:0] bits (PLL multiplication factor).
	PLLMUL_0    CFGR = 0x01 << 18 //  Bit 0.
	PLLMUL_1    CFGR = 0x02 << 18 //  Bit 1.
	PLLMUL_2    CFGR = 0x04 << 18 //  Bit 2.
	PLLMUL_3    CFGR = 0x08 << 18 //  Bit 3.
	PLLMUL3     CFGR = 0x00 << 18 //  PLL input clock * 3.
	PLLMUL4     CFGR = 0x01 << 18 //  PLL input clock * 4.
	PLLMUL6     CFGR = 0x02 << 18 //  PLL input clock * 6.
	PLLMUL8     CFGR = 0x03 << 18 //  PLL input clock * 8.
	PLLMUL12    CFGR = 0x04 << 18 //  PLL input clock * 12.
	PLLMUL16    CFGR = 0x05 << 18 //  PLL input clock * 16.
	PLLMUL24    CFGR = 0x06 << 18 //  PLL input clock * 24.
	PLLMUL32    CFGR = 0x07 << 18 //  PLL input clock * 32.
	PLLMUL48    CFGR = 0x08 << 18 //  PLL input clock * 48.
	PLLDIV      CFGR = 0x03 << 22 //+ PLLDIV[1:0] bits (PLL Output Division).
	PLLDIV_0    CFGR = 0x01 << 22 //  Bit0.
	PLLDIV_1    CFGR = 0x02 << 22 //  Bit1.
	PLLDIV1     CFGR = 0x00 << 22 //  PLL clock output = CKVCO / 1.
	PLLDIV2     CFGR = 0x01 << 22 //  PLL clock output = CKVCO / 2.
	PLLDIV3     CFGR = 0x02 << 22 //  PLL clock output = CKVCO / 3.
	PLLDIV4     CFGR = 0x03 << 22 //  PLL clock output = CKVCO / 4.
	MCOSEL      CFGR = 0x07 << 24 //+ MCO[2:0] bits (Microcontroller Clock Output).
	MCOSEL_0    CFGR = 0x01 << 24 //  Bit 0.
	MCOSEL_1    CFGR = 0x02 << 24 //  Bit 1.
	MCOSEL_2    CFGR = 0x04 << 24 //  Bit 2.
	MCO_NOCLOCK CFGR = 0x00 << 24 //  No clock.
	MCO_SYSCLK  CFGR = 0x01 << 24 //  System clock selected.
	MCO_HSI     CFGR = 0x02 << 24 //  Internal 16 MHz RC oscillator clock selected.
	MCO_MSI     CFGR = 0x03 << 24 //  Internal Medium Speed RC oscillator clock selected.
	MCO_HSE     CFGR = 0x04 << 24 //  External 1-25 MHz oscillator clock selected.
	MCO_PLL     CFGR = 0x05 << 24 //  PLL clock divided.
	MCO_LSI     CFGR = 0x06 << 24 //  LSI selected.
	MCO_LSE     CFGR = 0x07 << 24 //  LSE selected.
	MCOPRE      CFGR = 0x07 << 28 //+ MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler).
	MCOPRE_0    CFGR = 0x01 << 28 //  Bit 0.
	MCOPRE_1    CFGR = 0x02 << 28 //  Bit 1.
	MCOPRE_2    CFGR = 0x04 << 28 //  Bit 2.
	MCO_DIV1    CFGR = 0x00 << 28 //  MCO Clock divided by 1.
	MCO_DIV2    CFGR = 0x01 << 28 //  MCO Clock divided by 2.
	MCO_DIV4    CFGR = 0x02 << 28 //  MCO Clock divided by 4.
	MCO_DIV8    CFGR = 0x03 << 28 //  MCO Clock divided by 8.
	MCO_DIV16   CFGR = 0x04 << 28 //  MCO Clock divided by 16.
)

const (
	SWn     = 0
	SWSn    = 2
	HPREn   = 4
	PPRE1n  = 8
	PPRE2n  = 11
	PLLSRCn = 16
	PLLMULn = 18
	PLLDIVn = 22
	MCOSELn = 24
	MCOPREn = 28
)

const (
	LSIRDYF  CIR = 0x01 << 0  //+ LSI Ready Interrupt flag.
	LSERDYF  CIR = 0x01 << 1  //+ LSE Ready Interrupt flag.
	HSIRDYF  CIR = 0x01 << 2  //+ HSI Ready Interrupt flag.
	HSERDYF  CIR = 0x01 << 3  //+ HSE Ready Interrupt flag.
	PLLRDYF  CIR = 0x01 << 4  //+ PLL Ready Interrupt flag.
	MSIRDYF  CIR = 0x01 << 5  //+ MSI Ready Interrupt flag.
	LSECSS   CIR = 0x01 << 6  //+ LSE CSS Interrupt flag.
	CSSF     CIR = 0x01 << 7  //+ Clock Security System Interrupt flag.
	LSIRDYIE CIR = 0x01 << 8  //+ LSI Ready Interrupt Enable.
	LSERDYIE CIR = 0x01 << 9  //+ LSE Ready Interrupt Enable.
	HSIRDYIE CIR = 0x01 << 10 //+ HSI Ready Interrupt Enable.
	HSERDYIE CIR = 0x01 << 11 //+ HSE Ready Interrupt Enable.
	PLLRDYIE CIR = 0x01 << 12 //+ PLL Ready Interrupt Enable.
	MSIRDYIE CIR = 0x01 << 13 //+ MSI Ready Interrupt Enable.
	LSECSSIE CIR = 0x01 << 14 //+ LSE CSS Interrupt Enable.
	LSIRDYC  CIR = 0x01 << 16 //+ LSI Ready Interrupt Clear.
	LSERDYC  CIR = 0x01 << 17 //+ LSE Ready Interrupt Clear.
	HSIRDYC  CIR = 0x01 << 18 //+ HSI Ready Interrupt Clear.
	HSERDYC  CIR = 0x01 << 19 //+ HSE Ready Interrupt Clear.
	PLLRDYC  CIR = 0x01 << 20 //+ PLL Ready Interrupt Clear.
	MSIRDYC  CIR = 0x01 << 21 //+ MSI Ready Interrupt Clear.
	LSECSSC  CIR = 0x01 << 22 //+ LSE CSS Interrupt Clear.
	CSSC     CIR = 0x01 << 23 //+ Clock Security System Interrupt Clear.
)

const (
	LSIRDYFn  = 0
	LSERDYFn  = 1
	HSIRDYFn  = 2
	HSERDYFn  = 3
	PLLRDYFn  = 4
	MSIRDYFn  = 5
	LSECSSn   = 6
	CSSFn     = 7
	LSIRDYIEn = 8
	LSERDYIEn = 9
	HSIRDYIEn = 10
	HSERDYIEn = 11
	PLLRDYIEn = 12
	MSIRDYIEn = 13
	LSECSSIEn = 14
	LSIRDYCn  = 16
	LSERDYCn  = 17
	HSIRDYCn  = 18
	HSERDYCn  = 19
	PLLRDYCn  = 20
	MSIRDYCn  = 21
	LSECSSCn  = 22
	CSSCn     = 23
)

const (
	GPIOARST AHBRSTR = 0x01 << 0  //+ GPIO port A reset.
	GPIOBRST AHBRSTR = 0x01 << 1  //+ GPIO port B reset.
	GPIOCRST AHBRSTR = 0x01 << 2  //+ GPIO port C reset.
	GPIODRST AHBRSTR = 0x01 << 3  //+ GPIO port D reset.
	GPIOERST AHBRSTR = 0x01 << 4  //+ GPIO port E reset.
	GPIOHRST AHBRSTR = 0x01 << 5  //+ GPIO port H reset.
	GPIOFRST AHBRSTR = 0x01 << 6  //+ GPIO port F reset.
	GPIOGRST AHBRSTR = 0x01 << 7  //+ GPIO port G reset.
	CRCRST   AHBRSTR = 0x01 << 12 //+ CRC reset.
	FLITFRST AHBRSTR = 0x01 << 15 //+ FLITF reset.
	DMA1RST  AHBRSTR = 0x01 << 24 //+ DMA1 reset.
	DMA2RST  AHBRSTR = 0x01 << 25 //+ DMA2 reset.
	AESRST   AHBRSTR = 0x01 << 27 //+ AES reset.
	FSMCRST  AHBRSTR = 0x01 << 30 //+ FSMC reset.
)

const (
	GPIOARSTn = 0
	GPIOBRSTn = 1
	GPIOCRSTn = 2
	GPIODRSTn = 3
	GPIOERSTn = 4
	GPIOHRSTn = 5
	GPIOFRSTn = 6
	GPIOGRSTn = 7
	CRCRSTn   = 12
	FLITFRSTn = 15
	DMA1RSTn  = 24
	DMA2RSTn  = 25
	AESRSTn   = 27
	FSMCRSTn  = 30
)

const (
	SYSCFGRST APB2RSTR = 0x01 << 0  //+ System Configuration SYSCFG reset.
	TIM9RST   APB2RSTR = 0x01 << 2  //+ TIM9 reset.
	TIM10RST  APB2RSTR = 0x01 << 3  //+ TIM10 reset.
	TIM11RST  APB2RSTR = 0x01 << 4  //+ TIM11 reset.
	ADC1RST   APB2RSTR = 0x01 << 9  //+ ADC1 reset.
	SDIORST   APB2RSTR = 0x01 << 11 //+ SDIO reset.
	SPI1RST   APB2RSTR = 0x01 << 12 //+ SPI1 reset.
	USART1RST APB2RSTR = 0x01 << 14 //+ USART1 reset.
)

const (
	SYSCFGRSTn = 0
	TIM9RSTn   = 2
	TIM10RSTn  = 3
	TIM11RSTn  = 4
	ADC1RSTn   = 9
	SDIORSTn   = 11
	SPI1RSTn   = 12
	USART1RSTn = 14
)

const (
	TIM2RST   APB1RSTR = 0x01 << 0  //+ Timer 2 reset.
	TIM3RST   APB1RSTR = 0x01 << 1  //+ Timer 3 reset.
	TIM4RST   APB1RSTR = 0x01 << 2  //+ Timer 4 reset.
	TIM5RST   APB1RSTR = 0x01 << 3  //+ Timer 5 reset.
	TIM6RST   APB1RSTR = 0x01 << 4  //+ Timer 6 reset.
	TIM7RST   APB1RSTR = 0x01 << 5  //+ Timer 7 reset.
	LCDRST    APB1RSTR = 0x01 << 9  //+ LCD reset.
	WWDGRST   APB1RSTR = 0x01 << 11 //+ Window Watchdog reset.
	SPI2RST   APB1RSTR = 0x01 << 14 //+ SPI 2 reset.
	SPI3RST   APB1RSTR = 0x01 << 15 //+ SPI 3 reset.
	USART2RST APB1RSTR = 0x01 << 17 //+ USART 2 reset.
	USART3RST APB1RSTR = 0x01 << 18 //+ USART 3 reset.
	UART4RST  APB1RSTR = 0x01 << 19 //+ UART 4 reset.
	UART5RST  APB1RSTR = 0x01 << 20 //+ UART 5 reset.
	I2C1RST   APB1RSTR = 0x01 << 21 //+ I2C 1 reset.
	I2C2RST   APB1RSTR = 0x01 << 22 //+ I2C 2 reset.
	USBRST    APB1RSTR = 0x01 << 23 //+ USB reset.
	PWRRST    APB1RSTR = 0x01 << 28 //+ Power interface reset.
	DACRST    APB1RSTR = 0x01 << 29 //+ DAC interface reset.
	COMPRST   APB1RSTR = 0x01 << 31 //+ Comparator interface reset.
)

const (
	TIM2RSTn   = 0
	TIM3RSTn   = 1
	TIM4RSTn   = 2
	TIM5RSTn   = 3
	TIM6RSTn   = 4
	TIM7RSTn   = 5
	LCDRSTn    = 9
	WWDGRSTn   = 11
	SPI2RSTn   = 14
	SPI3RSTn   = 15
	USART2RSTn = 17
	USART3RSTn = 18
	UART4RSTn  = 19
	UART5RSTn  = 20
	I2C1RSTn   = 21
	I2C2RSTn   = 22
	USBRSTn    = 23
	PWRRSTn    = 28
	DACRSTn    = 29
	COMPRSTn   = 31
)

const (
	GPIOAEN AHBENR = 0x01 << 0  //+ GPIO port A clock enable.
	GPIOBEN AHBENR = 0x01 << 1  //+ GPIO port B clock enable.
	GPIOCEN AHBENR = 0x01 << 2  //+ GPIO port C clock enable.
	GPIODEN AHBENR = 0x01 << 3  //+ GPIO port D clock enable.
	GPIOEEN AHBENR = 0x01 << 4  //+ GPIO port E clock enable.
	GPIOHEN AHBENR = 0x01 << 5  //+ GPIO port H clock enable.
	GPIOFEN AHBENR = 0x01 << 6  //+ GPIO port F clock enable.
	GPIOGEN AHBENR = 0x01 << 7  //+ GPIO port G clock enable.
	CRCEN   AHBENR = 0x01 << 12 //+ CRC clock enable.
	FLITFEN AHBENR = 0x01 << 15 //+ FLITF clock enable (has effect only when.
	DMA1EN  AHBENR = 0x01 << 24 //+ DMA1 clock enable.
	DMA2EN  AHBENR = 0x01 << 25 //+ DMA2 clock enable.
	AESEN   AHBENR = 0x01 << 27 //+ AES clock enable.
	FSMCEN  AHBENR = 0x01 << 30 //+ FSMC clock enable.
)

const (
	GPIOAENn = 0
	GPIOBENn = 1
	GPIOCENn = 2
	GPIODENn = 3
	GPIOEENn = 4
	GPIOHENn = 5
	GPIOFENn = 6
	GPIOGENn = 7
	CRCENn   = 12
	FLITFENn = 15
	DMA1ENn  = 24
	DMA2ENn  = 25
	AESENn   = 27
	FSMCENn  = 30
)

const (
	SYSCFGEN APB2ENR = 0x01 << 0  //+ System Configuration SYSCFG clock enable.
	TIM9EN   APB2ENR = 0x01 << 2  //+ TIM9 interface clock enable.
	TIM10EN  APB2ENR = 0x01 << 3  //+ TIM10 interface clock enable.
	TIM11EN  APB2ENR = 0x01 << 4  //+ TIM11 Timer clock enable.
	ADC1EN   APB2ENR = 0x01 << 9  //+ ADC1 clock enable.
	SDIOEN   APB2ENR = 0x01 << 11 //+ SDIO clock enable.
	SPI1EN   APB2ENR = 0x01 << 12 //+ SPI1 clock enable.
	USART1EN APB2ENR = 0x01 << 14 //+ USART1 clock enable.
)

const (
	SYSCFGENn = 0
	TIM9ENn   = 2
	TIM10ENn  = 3
	TIM11ENn  = 4
	ADC1ENn   = 9
	SDIOENn   = 11
	SPI1ENn   = 12
	USART1ENn = 14
)

const (
	TIM2EN   APB1ENR = 0x01 << 0  //+ Timer 2 clock enabled.
	TIM3EN   APB1ENR = 0x01 << 1  //+ Timer 3 clock enable.
	TIM4EN   APB1ENR = 0x01 << 2  //+ Timer 4 clock enable.
	TIM5EN   APB1ENR = 0x01 << 3  //+ Timer 5 clock enable.
	TIM6EN   APB1ENR = 0x01 << 4  //+ Timer 6 clock enable.
	TIM7EN   APB1ENR = 0x01 << 5  //+ Timer 7 clock enable.
	LCDEN    APB1ENR = 0x01 << 9  //+ LCD clock enable.
	WWDGEN   APB1ENR = 0x01 << 11 //+ Window Watchdog clock enable.
	SPI2EN   APB1ENR = 0x01 << 14 //+ SPI 2 clock enable.
	SPI3EN   APB1ENR = 0x01 << 15 //+ SPI 3 clock enable.
	USART2EN APB1ENR = 0x01 << 17 //+ USART 2 clock enable.
	USART3EN APB1ENR = 0x01 << 18 //+ USART 3 clock enable.
	UART4EN  APB1ENR = 0x01 << 19 //+ UART 4 clock enable.
	UART5EN  APB1ENR = 0x01 << 20 //+ UART 5 clock enable.
	I2C1EN   APB1ENR = 0x01 << 21 //+ I2C 1 clock enable.
	I2C2EN   APB1ENR = 0x01 << 22 //+ I2C 2 clock enable.
	USBEN    APB1ENR = 0x01 << 23 //+ USB clock enable.
	PWREN    APB1ENR = 0x01 << 28 //+ Power interface clock enable.
	DACEN    APB1ENR = 0x01 << 29 //+ DAC interface clock enable.
	COMPEN   APB1ENR = 0x01 << 31 //+ Comparator interface clock enable.
)

const (
	TIM2ENn   = 0
	TIM3ENn   = 1
	TIM4ENn   = 2
	TIM5ENn   = 3
	TIM6ENn   = 4
	TIM7ENn   = 5
	LCDENn    = 9
	WWDGENn   = 11
	SPI2ENn   = 14
	SPI3ENn   = 15
	USART2ENn = 17
	USART3ENn = 18
	UART4ENn  = 19
	UART5ENn  = 20
	I2C1ENn   = 21
	I2C2ENn   = 22
	USBENn    = 23
	PWRENn    = 28
	DACENn    = 29
	COMPENn   = 31
)

const (
	GPIOALPEN AHBLPENR = 0x01 << 0  //+ GPIO port A clock enabled in sleep mode.
	GPIOBLPEN AHBLPENR = 0x01 << 1  //+ GPIO port B clock enabled in sleep mode.
	GPIOCLPEN AHBLPENR = 0x01 << 2  //+ GPIO port C clock enabled in sleep mode.
	GPIODLPEN AHBLPENR = 0x01 << 3  //+ GPIO port D clock enabled in sleep mode.
	GPIOELPEN AHBLPENR = 0x01 << 4  //+ GPIO port E clock enabled in sleep mode.
	GPIOHLPEN AHBLPENR = 0x01 << 5  //+ GPIO port H clock enabled in sleep mode.
	GPIOFLPEN AHBLPENR = 0x01 << 6  //+ GPIO port F clock enabled in sleep mode.
	GPIOGLPEN AHBLPENR = 0x01 << 7  //+ GPIO port G clock enabled in sleep mode.
	CRCLPEN   AHBLPENR = 0x01 << 12 //+ CRC clock enabled in sleep mode.
	FLITFLPEN AHBLPENR = 0x01 << 15 //+ Flash Interface clock enabled in sleep mode.
	SRAMLPEN  AHBLPENR = 0x01 << 16 //+ SRAM clock enabled in sleep mode.
	DMA1LPEN  AHBLPENR = 0x01 << 24 //+ DMA1 clock enabled in sleep mode.
	DMA2LPEN  AHBLPENR = 0x01 << 25 //+ DMA2 clock enabled in sleep mode.
	AESLPEN   AHBLPENR = 0x01 << 27 //+ AES clock enabled in sleep mode.
	FSMCLPEN  AHBLPENR = 0x01 << 30 //+ FSMC clock enabled in sleep mode.
)

const (
	GPIOALPENn = 0
	GPIOBLPENn = 1
	GPIOCLPENn = 2
	GPIODLPENn = 3
	GPIOELPENn = 4
	GPIOHLPENn = 5
	GPIOFLPENn = 6
	GPIOGLPENn = 7
	CRCLPENn   = 12
	FLITFLPENn = 15
	SRAMLPENn  = 16
	DMA1LPENn  = 24
	DMA2LPENn  = 25
	AESLPENn   = 27
	FSMCLPENn  = 30
)

const (
	SYSCFGLPEN APB2LPENR = 0x01 << 0  //+ System Configuration SYSCFG clock enabled in sleep mode.
	TIM9LPEN   APB2LPENR = 0x01 << 2  //+ TIM9 interface clock enabled in sleep mode.
	TIM10LPEN  APB2LPENR = 0x01 << 3  //+ TIM10 interface clock enabled in sleep mode.
	TIM11LPEN  APB2LPENR = 0x01 << 4  //+ TIM11 Timer clock enabled in sleep mode.
	ADC1LPEN   APB2LPENR = 0x01 << 9  //+ ADC1 clock enabled in sleep mode.
	SDIOLPEN   APB2LPENR = 0x01 << 11 //+ SDIO clock enabled in sleep mode.
	SPI1LPEN   APB2LPENR = 0x01 << 12 //+ SPI1 clock enabled in sleep mode.
	USART1LPEN APB2LPENR = 0x01 << 14 //+ USART1 clock enabled in sleep mode.
)

const (
	SYSCFGLPENn = 0
	TIM9LPENn   = 2
	TIM10LPENn  = 3
	TIM11LPENn  = 4
	ADC1LPENn   = 9
	SDIOLPENn   = 11
	SPI1LPENn   = 12
	USART1LPENn = 14
)

const (
	TIM2LPEN   APB1LPENR = 0x01 << 0  //+ Timer 2 clock enabled in sleep mode.
	TIM3LPEN   APB1LPENR = 0x01 << 1  //+ Timer 3 clock enabled in sleep mode.
	TIM4LPEN   APB1LPENR = 0x01 << 2  //+ Timer 4 clock enabled in sleep mode.
	TIM5LPEN   APB1LPENR = 0x01 << 3  //+ Timer 5 clock enabled in sleep mode.
	TIM6LPEN   APB1LPENR = 0x01 << 4  //+ Timer 6 clock enabled in sleep mode.
	TIM7LPEN   APB1LPENR = 0x01 << 5  //+ Timer 7 clock enabled in sleep mode.
	LCDLPEN    APB1LPENR = 0x01 << 9  //+ LCD clock enabled in sleep mode.
	WWDGLPEN   APB1LPENR = 0x01 << 11 //+ Window Watchdog clock enabled in sleep mode.
	SPI2LPEN   APB1LPENR = 0x01 << 14 //+ SPI 2 clock enabled in sleep mode.
	SPI3LPEN   APB1LPENR = 0x01 << 15 //+ SPI 3 clock enabled in sleep mode.
	USART2LPEN APB1LPENR = 0x01 << 17 //+ USART 2 clock enabled in sleep mode.
	USART3LPEN APB1LPENR = 0x01 << 18 //+ USART 3 clock enabled in sleep mode.
	UART4LPEN  APB1LPENR = 0x01 << 19 //+ UART 4 clock enabled in sleep mode.
	UART5LPEN  APB1LPENR = 0x01 << 20 //+ UART 5 clock enabled in sleep mode.
	I2C1LPEN   APB1LPENR = 0x01 << 21 //+ I2C 1 clock enabled in sleep mode.
	I2C2LPEN   APB1LPENR = 0x01 << 22 //+ I2C 2 clock enabled in sleep mode.
	USBLPEN    APB1LPENR = 0x01 << 23 //+ USB clock enabled in sleep mode.
	PWRLPEN    APB1LPENR = 0x01 << 28 //+ Power interface clock enabled in sleep mode.
	DACLPEN    APB1LPENR = 0x01 << 29 //+ DAC interface clock enabled in sleep mode.
	COMPLPEN   APB1LPENR = 0x01 << 31 //+ Comparator interface clock enabled in sleep mode.
)

const (
	TIM2LPENn   = 0
	TIM3LPENn   = 1
	TIM4LPENn   = 2
	TIM5LPENn   = 3
	TIM6LPENn   = 4
	TIM7LPENn   = 5
	LCDLPENn    = 9
	WWDGLPENn   = 11
	SPI2LPENn   = 14
	SPI3LPENn   = 15
	USART2LPENn = 17
	USART3LPENn = 18
	UART4LPENn  = 19
	UART5LPENn  = 20
	I2C1LPENn   = 21
	I2C2LPENn   = 22
	USBLPENn    = 23
	PWRLPENn    = 28
	DACLPENn    = 29
	COMPLPENn   = 31
)

const (
	LSION          CSR = 0x01 << 0  //+ Internal Low Speed oscillator enable.
	LSIRDY         CSR = 0x01 << 1  //+ Internal Low Speed oscillator Ready.
	LSEON          CSR = 0x01 << 8  //+ External Low Speed oscillator enable.
	LSERDY         CSR = 0x01 << 9  //+ External Low Speed oscillator Ready.
	LSEBYP         CSR = 0x01 << 10 //+ External Low Speed oscillator Bypass.
	LSECSSON       CSR = 0x01 << 11 //+ External Low Speed oscillator CSS Enable.
	LSECSSD        CSR = 0x01 << 12 //+ External Low Speed oscillator CSS Detected.
	RTCSEL         CSR = 0x03 << 16 //+ RTCSEL[1:0] bits (RTC clock source selection).
	RTCSEL_0       CSR = 0x01 << 16 //  Bit 0.
	RTCSEL_1       CSR = 0x02 << 16 //  Bit 1.
	RTCSEL_NOCLOCK CSR = 0x00 << 16 //  No clock.
	RTCSEL_LSE     CSR = 0x01 << 16 //  LSE oscillator clock used as RTC clock.
	RTCSEL_LSI     CSR = 0x02 << 16 //  LSI oscillator clock used as RTC clock.
	RTCSEL_HSE     CSR = 0x03 << 16 //  HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock.
	RTCEN          CSR = 0x01 << 22 //+ RTC clock enable.
	RTCRST         CSR = 0x01 << 23 //+ RTC reset.
	RMVF           CSR = 0x01 << 24 //+ Remove reset flag.
	OBLRSTF        CSR = 0x01 << 25 //+ Option Bytes Loader reset flag.
	PINRSTF        CSR = 0x01 << 26 //+ PIN reset flag.
	PORRSTF        CSR = 0x01 << 27 //+ POR/PDR reset flag.
	SFTRSTF        CSR = 0x01 << 28 //+ Software Reset flag.
	IWDGRSTF       CSR = 0x01 << 29 //+ Independent Watchdog reset flag.
	WWDGRSTF       CSR = 0x01 << 30 //+ Window watchdog reset flag.
	LPWRRSTF       CSR = 0x01 << 31 //+ Low-Power reset flag.
)

const (
	LSIONn    = 0
	LSIRDYn   = 1
	LSEONn    = 8
	LSERDYn   = 9
	LSEBYPn   = 10
	LSECSSONn = 11
	LSECSSDn  = 12
	RTCSELn   = 16
	RTCENn    = 22
	RTCRSTn   = 23
	RMVFn     = 24
	OBLRSTFn  = 25
	PINRSTFn  = 26
	PORRSTFn  = 27
	SFTRSTFn  = 28
	IWDGRSTFn = 29
	WWDGRSTFn = 30
	LPWRRSTFn = 31
)
